The design of a computer system may be broken down into three parts system design, logic design, and circuit design. System design involves breaking the overall system into subsystems and specifying the characteristics of each subsystem. For example, system design of a computer system could involve specifying the number and type of memory units, arithmetic units, and input-output devices as well as the interconnection and control of these subsystems. Logic design involves determining how to interconnect basic logic building blocks to perform a specific function. An example of logic design is determining the interconnection of logic gates and flip-flops to perform binary addition. Circuit design involves specifying the interconnection of specific components such as resistors, diodes, and transistors to form a gate, flip-flop, or other logic building block.
There are various logic families that are used in circuit design. Each family has its own capabilities and limitations. Diode logic (xe2x80x9cDLxe2x80x9d) families use diodes to perform certain logic functions. The use of DL families is simple and inexpensive, and can be used effectively in specific situations. Resistor-transistor logic (xe2x80x9cRTLxe2x80x9d) families use resistors to combine multiple input signals and a transistor to amplify and invert the resulting combined signal. Like the DL families, the use of RTL families is simple and inexpensive. In addition, they are also useful because both normal and inverted signals are usually available. Diode-transistor logic (xe2x80x9cDTLxe2x80x9d) families use DL combined with a transistor at the output in order to provide logic inversion and to restore a signal to full logic levels. Transistor-transistor logic (xe2x80x9cTTLxe2x80x9d) families replace all input diodes in DTL with transistors. Emitter-coupled logic (xe2x80x9cECLxe2x80x9d) families are designed to operate at extremely high speeds by avoiding delays that are inherent when a transistor becomes saturated. Complementary metal-oxide-semiconductor (xe2x80x9cCMOSxe2x80x9d) logic families use metal-oxide-semiconductor field-effect transistors (xe2x80x9cMOSFETsxe2x80x9d).
The use of MOSFET transistors is beneficial because lower currents are needed to operate these transistors than other types of devices. However, MOSFETs operate slower than devices used in other logic families. MOSFETs may be divided into two types of transistors: positive-channel metal-oxide semiconductor (xe2x80x9cPMOSxe2x80x9d) transistors and negative-channel metal-oxide semiconductor (xe2x80x9cNMOSxe2x80x9d) transistors. A transistor is xe2x80x98onxe2x80x99 when there is an electrical pathway across the transistor such that a voltage at one terminal of the transistor can be seen at another terminal of the transistor. NMOS transistors can be switched xe2x80x98onxe2x80x99 or xe2x80x98offxe2x80x99 by the movement of electrons, whereas PMOS transistors can be switched xe2x80x98onxe2x80x99 or xe2x80x98offxe2x80x99 by the movement of electron vacancies. Every MOSFET has a voltage threshold (xe2x80x9cVTxe2x80x9d) value, which is the voltage level at which the MOSFET switches xe2x80x98onxe2x80x99 or xe2x80x98off.xe2x80x99 Generally, a NMOS transistor switches xe2x80x98onxe2x80x99 when there is a high voltage applied to a gate terminal of the NMOS transistor and a PMOS transistor switches xe2x80x98onxe2x80x99 when there is a low voltage, e.g., ground, applied to a gate terminal of the PMOS transistor. Moreover, for the purposes of this application, the gate terminal of a MOSFET transistor will be referred to as the xe2x80x9cinputxe2x80x9d of the transistor.
Like other logic families, CMOS logic families may be divided into two categories: static logic and dynamic logic. Static logic is logic in which the function of a circuit is not synchronized by a global signal, e.g., a clock signal. The output of the circuit is solely a function of the input to the circuit. Moreover, the output is asynchronous with respect to the input. Dynamic logic is logic in which the output of a circuit is synchronized by a global signal. Therefore, the output of a dynamic circuit is a function of both the input(s) to the circuit and the global signal.
An example of a CMOS logic family is CMOS buffer logic. Buffer logic is necessary in order to restore signals to full voltage levels. For example, a signal that should be at 5 volts may only be at 4 volts at a specific point in a circuit due to voltage dissipation. In order to ensure that a signal is at its true desired voltage level, a buffer inputs the signal and outputs a restored signal with a full voltage level. Alternatively, buffer logic can also be used to restore a 0 volt signal. Also, buffer logic can be used to set a signal to a desired voltage that is different in value from a full voltage level value.
FIG. 1 shows a prior art embodiment of static buffer logic that uses CMOS transistors. The static buffer (10) includes an input, INPUT_1, followed by two cascaded transistor pairs. The first pair of transistors (xe2x80x9cthe first pairxe2x80x9d), the pair of transistors that immediately follows INPUT_1, includes a PMOS transistor (12) (referred to hereafter as xe2x80x9cthe PMOS transistor (12) in the first pairxe2x80x9d) and a NMOS transistor (14) (referred to hereafter as xe2x80x9cthe NMOS transistor (14) in the first pairxe2x80x9d). INPUT_1 serves as an input to both the PMOS transistor (12) in the first pair and the NMOS transistor (14) in the first pair. The PMOS transistor (12) in the first pair has a terminal connected to a voltage source (13) (also referred to as xe2x80x9cconnected to highxe2x80x9d) and another terminal that is connected to both a terminal of the NMOS transistor (14) in the first pair and a node, BUFFER_NODE_1. The NMOS transistor (14) in the first pair, in addition to having a terminal that is connected to both a terminal of the PMOS transistor (12) in the first pair and BUFFER_NODE_1, has another terminal connected to ground (15) (also referred to as xe2x80x9cconnected to lowxe2x80x9d).
The second pair of transistors (xe2x80x9cthe second pairxe2x80x9d), the pair of transistors that follows the first pair of transistors, also includes a PMOS transistor (16) (referred to hereafter as xe2x80x9cthe PMOS transistor (16) in the second pair) and a NMOS transistor (18) (referred to hereafter as xe2x80x9cthe NMOS transistor (18) in the second pairxe2x80x9d). BUFFER_NODE_1 serves as an input to both the PMOS transistor (16) in the second pair and the NMOS transistor (18) in the second pair. The PMOS transistor (16) in the second pair has a terminal connected to high (13) and another terminal that is connected to both a terminal of the NMOS transistor (18) in the second pair and the output of the static buffer (10), OUTPUT_1. The NMOS transistor (18) in the second pair, in addition to having a terminal that is connected to the PMOS transistor (16) in the second pair and OUTPUT_1, has another terminal connected to low (15).
When there is a rising edge, i.e., high, at INPUT_1, the PMOS transistor (12) in the first pair switches xe2x80x98offxe2x80x99 and the NMOS transistor (14) in the first pair switches xe2x80x98on.xe2x80x99 Since the NMOS transistor (14) in the first pair switches xe2x80x98on,xe2x80x99 BUFFER_NODE_1 gets connected to low (15) through the NMOS transistor (14) in the first pair. As BUFFER_NODE_1 goes low, the PMOS transistor (16) in the second pair switches xe2x80x98onxe2x80x99 and the NMOS transistor (18) in the second pair switches xe2x80x98off.xe2x80x99 Since the PMOS transistor (16) in the second pair switches xe2x80x98on,xe2x80x99 OUTPUT_1 gets connected to high (13) through the PMOS transistor (16) in the second pair. Therefore, when INPUT_1 goes high, OUTPUT_1 follows and goes high restoring any voltage dissipation that may have been present at INPUT_1.
Alternatively, when there is a falling edge, i.e., low, at INPUT_1, the PMOS transistor (12) in the first pair switches xe2x80x98onxe2x80x99 and the NMOS transistor (14) in the first pair switches xe2x80x98off.xe2x80x99 Since the PMOS transistor (12) in the first pair switches xe2x80x98on,xe2x80x99 BUFFER_NODE_1 gets connected to high (13) through the PMOS transistor (12) in the first pair. As BUFFER_NODE_1 goes high, the PMOS transistor (16) in the second pair switches xe2x80x98offxe2x80x99 and the NMOS transistor (18) in the second pair switches xe2x80x98on.xe2x80x99 Since the NMOS transistor (18) in the second pair switches xe2x80x98on,xe2x80x99 OUTPUT_1 gets connected to low (15) through the NMOS transistor (18) in the second pair. Therefore, when INPUT_1 goes low, OUTPUT_1 follows and goes low removing any stray voltage that may have been present at INPUT_1. Thus, with respect to both cases when INPUT_1 is either high or low, the static buffer (10) shown in FIG. 1 is static because the output is solely a function of the input to the static buffer (10). Further, the static buffer (10) is designed such that both rising and falling edges at the input of the circuit trigger changes in the output of the circuit.
Another behavioral aspect of the static buffer (10) shown in FIG. 1 deals with the voltage and current activity at the output of the static buffer (10). When an input to the static buffer (10) goes low to high or high to low, there is a finite amount of time that both the PMOS transistor (16) in the second pair and the NMOS transistor (18) in the second pair are xe2x80x98on.xe2x80x99 This happens because MOSFET transistors cannot be instantaneously switched xe2x80x98offxe2x80x99 or xe2x80x98on.xe2x80x99 Thus, when an input to the static buffer (10) changes, current flows through both the PMOS transistor (16) in the second pair and the NMOS transistor (18) in the second pair, and this causes what is known in the art as a xe2x80x9ccrow barxe2x80x9d effect, i.e., a short circuit, at the output of the static buffer. Generally, this xe2x80x9ccrow barxe2x80x9d effect is not desired because it causes the output to switch more slowly and lose power.
Relative to static logic, which is exemplified by the static buffer (10) in FIG. 1, dynamic logic operates faster. However, dynamic logic functions are monotonic, i.e., functions are triggered either by a rising edge or falling edge, but not both. In addition, typical dynamic logic uses a pre-charge transistor to lead the circuit to a known state to ensure a stable output.
FIG. 2 shows a prior art embodiment of a single-edge triggered dynamic circuit (20) that can be used as a buffer. The single-edge triggered dynamic circuit (20), also known in the art as a xe2x80x9cpost-charge logic stage,xe2x80x9d includes an input, INPUT_2, which serves as an input to both a first PMOS transistor (22) and a NMOS transistor (26). The first PMOS transistor (22) has a terminal connected to high (13) and has another terminal connected to a node, BUFFER_NODE_2. The NMOS transistor (26) has a terminal connected to low (15) and has another terminal that is connected to BUFFER_NODE_2. The first PMOS transistor (22) is in parallel with a second PMOS transistor (24), which has a terminal connected to high (13) and another terminal connected to BUFFER_NODE_2. BUFFER_NODE_2 is directly connected to the output of the single-edge triggered dynamic circuit (20), OUTPUT_2, and also serves as an input to a chain of four inverters in series (28, 30, 32, 34). The output of the fourth inverter (34) in the chain of the four inverters (28, 30, 32, 34) serves as an input to the second PMOS transistor (24).
Typically, INPUT_2 is pre-conditioned, i.e., pre-charged, low. Thereafter, INPUT_2 pulses high, causing the first PMOS transistor (22) to switch xe2x80x98offxe2x80x99 and the first NMOS transistor to switch xe2x80x98on.xe2x80x99 When the first NMOS transistor (26) switches xe2x80x98on,xe2x80x99 BUFFER_NODE_2 goes low because it gets connected to ground (15) through the first NMOS transistor (26). Accordingly, OUTPUT 2, which is tied to BUFFER_NODE _2 also goes low.
Furthermore, when BUFFER_NODE_2 goes low, the input to the first inverter (28), which is tied to BUFFER_NODE 2, also goes low. Because the first inverter (28) inputs low, the fourth inverter (34) outputs low to the input of the second PMOS transistor (24), which, in turn, causes the second PMOS transistor (24) to switch xe2x80x98on.xe2x80x99
Because the second PMOS transistor (24) switches xe2x80x98on,xe2x80x99 BUFFER_NODE_2 gets connected to high (13) through the second PMOS transistor (24). Accordingly, because BUFFER_NODE_2 goes high, OUTPUT_2 is reset back to high. However, because BUFFER_NODE_2 gets connected to high (13) through the second PMOS transistor (24), the first NMOS transistor (26) must switch xe2x80x98offxe2x80x99 before the second PMOS transistor (24) switches xe2x80x98on.xe2x80x99 Otherwise, a short circuit occurs between the high (13) and ground (15) terminals of the single-edge triggered dynamic circuit (20). Thus, before the second PMOS transistor (24) switches xe2x80x98on,xe2x80x99 INPUT_2 must go low to switch the first NMOS transistor (26) xe2x80x98off.xe2x80x99 Moreover, the purpose of the first PMOS transistor (22) is to hold OUTPUT_2 high when INPUT_2 is low.
An input signal that frequently needs to be buffered is a clock signal. Various circuits within a system are dependent upon the clock signal for purposes such as timing, signal alignment, toggling, etc. One characteristic of a clock signal deals with its duty cycle. The duty cycle of a signal denotes the fraction of time that a signal is active. For example, if a clock signal has a 50% duty cycle, then the signal is high for half the time in a given cycle and low for the other half of the time in the given cycle. One goal in buffering a clock signal is to try to as maintain the duty cycle of a clock signal such that the duty cycle of the clock signal at the output of a buffer is equal to the duty cycle of the clock signal at the input of the buffer. For example, in reference to FIG. 1, if there is a clock signal with a 50% duty cycle at INPUT_1, there will also be a clock signal with a 50% duty cycle at OUTPUT_1 since the static buffer (10) is triggered by both falling and rising edges at its input.
In reference to FIG. 2, if there is a clock signal with a 50% duty cycle at INPUT_2, the clock signal at OUTPUT_2 will have a duty cycle less than 50%. Essentially, this is because the circuit shown in FIG. 2 is triggered only by a single edge. At a rising edge of INPUT_2, OUTPUT_2 is triggered and follows low. However, INPUT_2 has to go low before OUTPUT_2 is reset back to high. Thus, OUTPUT_2 is low for a greater percentage of cycle time than is INPUT_2.
When a clock signal is separated into multiple signal paths for use by various circuits, the clock signal loses its strength. Therefore, computer systems incorporate clock distribution schemes in which a clock signal is split into multiple clock signals and then each clock signal is buffered before it is used as an input by a particular circuit within the system. Efficient and accurate buffers are needed in a clock distribution scheme to ensure that the duty cycle of a clock signal is not affected by the buffering in the clock distribution scheme. For example, in reference to FIG. 1, the static buffer (10) may be used in a clock distribution scheme since it maintains the same duty cycle at its input and output. However, the single-edge triggered dynamic circuit (20) cannot be used in a clock distribution scheme because its dynamic behavior does not maintain the same duty cycle at its input and output.
FIG. 3 shows a block diagram of a clock distribution scheme (40). The clock distribution scheme (40) includes a clock input, CLK, and n buffers (41, 42, 44, 46, 48) where n depends on the amount of clock buffers needed in a particular system. Typically, each buffer (41, 42, 44, 46, 48) outputs to a circuit that uses the clock output (CLK_OUTPUT_1, CLK_OUTPUT_2, CLK_OUTPUT_3, CLK_OUTPUT_4, CLK_OUTPUT_5) as an input. The clock distribution scheme (40) is desired in order to ensure that different circuits that use a clock signal as an input each get a full clock input signal as opposed to a clock signal that has stray voltages or is dissipated due to a poor clock distribution scheme that does not use buffers to strengthen the clock signal.
In one aspect, an output stage of a dynamic circuit comprises a first node that is triggered by a rising edge of an input signal, a second node that is triggered by a falling edge of the input signal, a first driver device that inputs a value on the first node, and a second driver device that inputs a value on the second node.
In another aspect, a dynamic circuit comprises a first control input stage that selectively triggers a first node on a rising edge of an input signal, a second control input stage that selectively triggers a second node on a falling edge of the input signal, and an output stage that generates an output signal based on values on the first and second nodes.
In another aspect, a method for an output stage of a dynamic circuit comprises inputting a first node to a first driver device, inputting a second node to a second driver device, selectively triggering the first node on a rising edge of an input signal, selectively triggering the second node on a falling edge of the input signal, and generating an output signal based on the first and second driver devices.
In another aspect, a method for performing dynamic circuit operations comprises inputting an input signal to a first control input stage that selectively controls a first node, inputting the input signal to a second control input stage that selectively controls a second node, selectively triggering the first node on a rising edge of the input signal, selectively triggering the second node on a falling edge of the input signal, and generating an output signal from an output stage dependent on the first and second nodes.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.